Tag Archives: FET

Jul. 11, 2013 SVForum After CMOS

SVFlogoWelser Jeff

On July 11, 2013 in San Francisco at Nixon Peabody, the SVForum Emerging Tech SIG hosted Dr. Jeffrey J. Welser, Director, Almaden Services Research & Accelerated Discovery Lab at IBM’s presentation “When Scaling Hits The End Of The Road.” Moore’s Law talks about ever increasing computing power for less cost. Welser talked about the physical limits of increasing the performance per dollar in semiconductor chips by scaling the dimensions of the field-effect transistor (FET) in Complimentary Metal Oxide Semiconductor (CMOS) technology. He then discussed newer logic devices, circuits and architecture that might be less volatile, use less power and easier to reconfigure.

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